At the 2013 International Test Conference, GOEPEL electronics will be demonstrating CION™ LX, the world’s first JTAG controllable Tester-on-Chip (ToC) with mixed signal architecture. The newly developed chip provides single-ended and differential test channels, which feature a Boundary Scan interface compliant with IEEE Std. 1149.1, IEEE Std.1149.6, or IEEE Std 1149.8.1. All channels can be coupled with numerous integrated analogue and digital instruments. As a result, the CION™ LX can support more than 15 different static and dynamic test and measurement operations on each test channel. In addition to classic Boundary Scan functionalities, these are arbitrary waveform generation, analogue signal recording, digital frequency measurement and toggle detection. In connection with programmable interface characteristics such as slew rate or pull up/down, the CION LX offers extremely flexible signal configuration and, therefore, necessary universality as a tester interface.
“The new CION LX helps to create universal scalable low-cost test systems that can easily be integrated into existing JTAG ecosystems, covering analogue and digital test and measurement tasks”, says Heiko Ehrenberg, Technology Officer for Embedded System Access (ESA) with GOEPEL electronics Ltd. USA. “The application focus is placed upon test quality improvement through deeper and more flexible structural tests and at-speed tests that don’t require high performant instrumentations. The utilized per pin architecture enables nearly unlimited implementations of mixed signal test strategies.”
About the CION™ LX:
The CION LX was developed in 0.35 µm mixed-signal CMOS technology and provides four independent I/O ports. Each port can be individually operated in a voltage range from 0.9 V to 3.6 V. The integrated Boundary Scan architecture supports the standards IEEE 1149.1, IEEE 1149.6 and IEEE 1149.8.1, at a maximum TCK frequency of 100 MHz. In addition to the single-ended pins, the CION LX provides differential signals as well as interfaces with increased driver ability. Four operation modes enable the IC‘s flexible utilization as purely serially controlled JTAG transceiver, parallel I/O buffer, latched bus transceiver, and pin driver.
Furthermore, instruments such as digitizer, arbitrary waveform generator, event counter, frequency meter and toggle detector are integrated into the CION LX. These instruments can be accessed – depending on operation mode – either serially via the JTAG Test Access Port (TAP) or a parallel control bus. The instruments can be activated simultaneously to Boundary Scan operations and per test channel. For each channel, pull-up and pull-down resistors can be additionally connected. Moreover, the drivers’ slew rates are programmable.
Availability and Licensing:
The CION LX is currently available as a sample. First series deliveries are planned for quarter three in 2013. An LGA housing with 116 pins will be used. Additionally, there will be a CION LX Evaluation Board.
About JTAG/Boundary Scan:
Boundary Scan (IEEE Std. 1149.x) is a modern access method for the test and programming of complex circuits without mechanical probe access (non-intrusive).
Boundary Scan is part of the Embedded System Access (ESA) strategies and is based on design-integrated test electronics. ESA technologies include techniques such as Chip Embedded Instruments, Processor Emulation Test, In-System Programming or Core Assisted Programming. They are currently the most modern strategies for validation, test and debug as well as programming of complex boards and systems. They can be applied throughout the entire product life cycle, enabling enhanced test coverage at reduced costs.